AGEMAME HQ

Today, I’d like to take you on a journey into the mind of a fruit machine PCB designer.

Picture the scene: you want to set up a 48 input system (16 on one bank, 16 on another and 16 DIP switches). You decide that it would be better to have them all run through one PIA, and have the selection timer controlled. So far so good, but it would be better if one bank of inputs was polled twice as fast.

The solution developed for MPU4 was to use a 74148 1 of 8 decoder to run 8 enable input lines, each line representing 8 of the 48 inputs. The bank that needed polling twice as fast was given two lines for each subbank, connected through an OR gate. This all makes sense so far, until you realise that there’s an OR gate on the side that is only being polled with one input line as well!

After much deliberation, it appears that the track for the second set of input lines has been split in two, so it will fit both entry points for the OR gate. I presume this is so that the input connectors only need to be fabricated once, rather than having two different designs.

The upshot of this is that AGEMAME now uses accurate input timing for the MPU4 system, although there are still some bugs to be worked out with the auxiliary connections which are direct links which bypass the timing circuitry.